ICdesign101.COM

Excellent in providing quality analog and Mixed Signal IP blocks, Design Automation Services, EDA/PDK flow/methodology design and review.

DESIGN QUALITY REVIEW
USEFUL LINK
  
                                                                                       Original created August 1 2009
                                                                                       Last Update      Sept. 7  2010  
                                                                                                           by Martin Chu

Company Info 

ICdesign101 is a small design and consulting service company that specialized in IC design quality and physical verification. We offers several consulting services range from physical verification services to ensure that your rule decks (Assura, Diva, Calibre or Dracule) are up-to-date, efficient and, most importantly, that they fully and correctly represent the manufacturing checks required by your process technology. This unique service is based upon a comprehensive understanding of the custom design flow from schematic entry to final chip assembly and physical verification. 

ICdesign101 can improve your physical verification cycle time by analyzing your existing verification methodology and by providing custom training in new technologies, or by offering our physical verification expertise to assist during your busiest time.

Services Provided

(a) Analog and Mixed Signal blocks Design

(b) Design project management 

(c) Indepent and third party Design block review and audit

(d) EDA flow and methodology design and/or review

Typical Projects

* Customize Calibre or Assura DRC, LVS, RCX deck development

* Pcell cdf and skill code development
CDK QC flow development
* Foundry DRC QA library buildup.
* Spice model and simulation validation
* Circuit simulation automation script
* Automatic SPICE model and simulation flow status report
* Design and Layout Automation review   
* Design and layout database version control and management
* Design flow and database/IP reuse methodology
consulting
* Commonly used ananlog and mixed signal block reuse methodology
* Pre-PG layout and circuit checklist and review 


For more Information

Contact us at 940 372 2172 , or send mail to martin.chu.20100406@gmail.com.




Useful Open Links

Cadence Assura Official Cadence Web page
Mixed Signal SOC design flow Mentor Mixed signal design flow doc
eg3 Best online embedded  and IP discssion group
Design-reuse Catalyst of Collaborative IP based SOC design
Demo on Demand Online demo from service providers
IC Design Quality Checklist IC design quality on design magazine.
DeepChip EDA group Online ESD discussion group. Lot of useful info.
OPENCORES Open source IP repository
Design/IP Reuse Online Design reuse and IP service provider
Agilent Online Demo Online Agilent EDA demo
Xilinx design reuse document Xilinx design resue Document.

IC design Business Intelligence and Competitive Advantages (Member Area)

Design Blocks
Silicon Design Zone Silicon Technology Zone
IP reuse issues Indusmridgegltry Outlook EDA prime


The arrangement of this website, some web contents and documents are copyrighted © 2010.    Martin Chu